Portable electronic devices such as mobile phones have become smaller and more compact. This evolution has led to smaller battery size that require less voltage than its previous version. ¹ There is also a growth of applications in wearable technology to enhance the quality of life through healthcare, education, security and many more. ^{2 – 5} As wearable designs grow, power and battery management become crucial, therefore there is a need to extend the battery life of a wearable design by employing energy efficient, while boosting circuit blocks. Different loads in the miniaturized wearable devices would require different operating voltages and load current which can be powered by battery through DC-DC converters. Converters are needed to regulate the voltage to the device requirement. There are two main types of converters which are electronic conversion and magnetic conversion. ⁶ Electronic conversion uses switching technology, while magnetic conversion utilizes magnetic field property in an inductor or a transformer. Most of the step-down DC-DC converters used in the system are buck converters. As the devices become smaller, a buck converter seems to be bulky, and its electromagnetic field becomes noisy due to the present of inductor in the circuit. ⁷ Magnetic field noise is bad for communication devices such as cell phones and laptops. ⁸ It also requires more components to build the circuit such as capacitor, diode, transistor as switch and sometimes it requires a filter to operate. Some of the problems include the size of buck converter, which is bulky due to multiple electronic components, compared to switched-capacitor converter. As for the inductor-based converter, it is dominantly noisy with magnetic field effects.

The focus of this project is to design a step-down converter circuit based on the switched-capacitor method which is smaller and cheaper. The design also focused on how to achieve higher efficiency to make it competitive compared to conventional inductor-based converter. This project also aims to minimize the number of electronic components used to reduce the cost. The project aims to use only capacitor and transistor as a switch in the circuit.

This section describes the methods used to complete the project including the design flow of the network, the circuit design, and the Electronic Design Automation (EDA) tools used. The design flow of this project is shown in Figure 1. The circuit is designed using complementary metal-oxide semiconductor (CMOS) 0.5um process using open-source EDA tools, namely LTSpice ^® software tool for schematic simulation and Electric very large-scale integration (VLSI) design tool for layout implementation.

The circuit or network as shown in Figure 2 has been designed using Kirchhoff Voltage Law (KVL) method, ⁹ which was divided into two phases: common phase and discharge phase. Common phase is the phase where the capacitor is charged and connected in parallel, while in discharge phase the capacitor is connected in parallel for the 1/2 gain region and in series for the 2/3 gain region.

Table 1 shows the switch cycle when the switches (S1 – S10) are turned on or off depending on the phase and gain regions.

This section discusses the results obtained in this project and compares these results to those of previous study findings. ^{10 – 12} Simulation results of the post layout implementation show that the high efficiency networks are achieved with low voltage drop and low internal resistance. The efficiency of the network is calculated and compared with other literature papers as shown in Table 2. In this work, efficiency is calculated based on the following equation. ¹³ Efficiency = Obtained output Expected output

The method is shown to be advantageous over previously developed analysis methods because of its simplicity.

From Table 2, the efficiency of this work or network is the highest compared to the other networks. The designed network used much less CMOS transistors compared to other networks. Hence, the designed network produced lower voltage drop across the transistor.

A multiple gain topology of DC-DC converter circuit for networks in the 1/2 and 2/3 voltage gain region using switched capacitor method has been designed with efficiency of 95% and 85%, respectively. This method has shown to be advantageous over previously developed analysis methods because of its simplicity. The network/circuit can be further improved by implementing clock cycle controller to control the phase of the clock in order to reduce any uncertainty at the output.

All data underlying the results are available as part of the article and no additional source data are required.

The authors declared that no human or animal experiments were involved in supporting this work.

Ahmad Khawarizmi performed data curation, formal analysis, investigation, methodology, software, validation, visualization, writing – original draft preparation. L. Lee performed conceptualization, data curation, methodology, project administration, resources, software, supervision, writing – original draft preparation, writing – review & editing.