Unlike the main building blocks such as the adders and parity checkers, routers form a crucial support system to the decoder. The routers’ function, mainly comprised of multiplexers and demultiplexers, helps arrange data bits according to the system configuration and passes the information through appropriate layers. Binary signals control multiplexers. ² The analogue MUX/DEMUX was designed using ternary inverters to control the circuits, and CMOS transmission gates were used. ^{6 – 8} The design improved and proved to be excellent for ternary inverters. With the idea of switching activities suggested by Anitha and Javachitra, ⁹ adiabatic logic reduces the power by offering back the stored energy to the supply and this was used for the 16:1 multiplexer and 1:16 demultiplexer. The results indicated that they had less power dissipation than conventional CMOS circuits. An 11 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL) was proposed by Ahn and Kim (2006). ¹⁰ The circuit received serial binary data, which was converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. This makes it possible to achieve higher operating speeds than that of conventional binary logic. The implemented DEMUX consisted of eight integrators and was designed with a 0.35 μm standard CMOS process. The DEMUX achieved the maximum data rate of 11 Gb/s and the average power consumption of 69.43 mW. This circuit was expected to operate faster than 11Gb/s in the high operating frequency’s deep-submicron process . A demultiplexer has been designed with 36 transistors using 90 nm CMOS technology. ⁷ Auto-generation technique and semi-custom layout design were integrated. There was an improvement in power consumption and area due to the semi-customized demultiplexer layout.

The multiplexer is a combinational logic circuit that selects an appropriate analogue (or) digital signal from several input signals and forwards it to a single output line. ¹¹ A multiplexer has several input lines and a single output line. The selection of the appropriate input is based on unique control lines called select lines. Figure 1 depicts a basic multiplexer with four inputs I ₀, I ₁, I ₂, I _3, and a single output line (Z). Multiplexers can be designed for a 2 ⁿ number of inputs. In this design, we used a 4 × 1 MUX because it is simpler to cascade these circuits for many inputs, and the decoder was also for 4-bit data. There are two select lines, S ₀, S ₁ which are the control lines of the circuit. The MUX is 4 × 1, representing four inputs and one output. An additional set of input lines control each input line’s selection according to these control input’s binary conditions, which indicated ‘HIGH’ (1) or ‘LOW’ (0). Multiplexers have an even number of 2 ⁿ data input lines and some control inputs that match the number of data inputs. The truth table for the 4 × 1 MUX is shown in Table 1.

The output Z is obtained from the Boolean expansion. Z = I 0 S 1 ¯ S 0 ¯ + I 1 S 1 ¯ S 0 + I 2 S 1 S 0 ¯ + I 3 S 1 S 0 . (1)

The equation (1) was expanded using associative and commutative laws to obtain an appropriate and optimized circuit equation for implementing the multiplexer. ¹¹ Any single input line is selected instantly depending on the combination of select lines input to be connected to the output Z. For example, if the select lines combination S ₁S ₀ is a logic ‘0’ a logic ‘1’ (01), then input line I ₁ would be connected to the output Z, referring to Table 1. Adding more control address lines (n) allowed the multiplexer to control more inputs to switch 2 ⁿ inputs. Still, each control line configuration will connect only one input to the output. In our proposed circuit, optimization of the circuit is done using pass transistor logic to design the multiplexer.

A 4 × 1 MUX was designed as shown in Figure 1, and the input to the multiplexer in this circuit was from a bit update block (BUB), part of the LDPC decoder structure. The inputs were from the 4-bit update units used in the decoder circuit designed for this research. The multiplexer aimed to receive the updated data bits from the bit update unit and rearrange the vectors according to the circuit’s requirements. ¹² The multiplexer circuit was designed using pass transistor logic. The MUX comprised NMOS and PMOS circuits for the inverters and only NMOS circuits for the remaining circuit. The inverter complemented the select input signals S ₀(S _A) and S ₁(S _B). The multiplexer was configured to have series-connected switches so that, based on the input combination of S ₀ and S ₁, one of the inputs was selected to pass the input to the output. The multiplexer passed a signal when the controlling voltage was logic low.

The circuit used NMOS because electron mobility is better than hole mobility, and hence the performance will be better. The inputs I ₀, I ₁, I ₂, and I ₃ fed from the 4-bit update circuits had the bit update unit’s computation values. The selection of the input that was given to the router was based on the select inputs S ₁ and S ₀. Inputs I ₀, I ₁, I ₂, and I ₃ were chosen to connect to the output line Z. Assuming the select inputs had an input combination of S ₀ = 0 and S ₁ = 1. The S ₀ input was fed to an inverter circuit formed by the pass transistors, which passed the value ‘0’ to the circuit, and the S ₁ with a logic ‘1’ was given to the other inverter circuit. The NMOS controlled the ground and the output in one inverter circuit, while PMOS connected the input supply V _DD and the output. ¹³ The transistors then did what they are best designed for, that is the NMOS allowed a logic ‘0’, and the PMOS allowed a logic ‘1’. It acted like a 2 × 1 MUX, where the inputs are logic 0 and logic 1. The input variable acted as the control signal and determined which input should be sent to the output. Hence, a combination of both inverters at the input would help select the signal sent to the output. This would be either I ₀, I ₁, I ₂, or I _3. In our example, I ₂ was fed to the output Z = I ₂.

Multiplexer design can be enlarged to have many more inputs by using the basic multiplexer circuits. A 16 × 1 MUX can be designed using 2 × 1, 4 × 1, and 8 × 1 MUX. As per basic MUX circuit design, 4 × 1 multiplexers are used so 16 inputs are available. Inputs I ₀ to I ₃ (for bits zero to three) are for the first multiplexer (to PMOS), I ₄ to I ₇ (for bits four to seven) to the second, and so on where the last multiplexer has inputs I ₁₂ to I ₁₅ (for bits 12 to 15). Every multiplexer’s select inputs are combined in parallel into two main selection lines that connect all four multiplexers. ^{14 , 15} The output from each multiplexer is now fed as four inputs to another 4 × 1 multiplexer. The output from this multiplexer becomes the main output of the circuit.

A demultiplexer is a combinational circuit that routes a single input line to multiple digital output lines. The demultiplexer of 2 ⁿ outputs has ‘n’ select lines to select which output lines need to be connected to the input. ^{13 , 14} In simple terms, it is a data distributor. The demultiplexer is a 1 × 4 unit, implying a single input line Y and four output lines, D ₀, D ₁, D _2, and D ₃. There are two select lines, S ₀ and S ₁. The select lines help to decide to which output line the input line Y should be connected. The select lines are controlled by the binary combination of 0 and 1. The select lines S ₀ and S ₁ can take on 00, 01, 10, and 11. These are the four possible combinations for two input signals and hence four possible output lines. The combination and connection of input Y to the output lines D ₀, D ₁, D _2, and D _3, follow the truth table given in Table 2. The data input to be connected to the particular output line is obtained from the equation, Y = S ¯ 1 S ¯ 0 D 0 + S 1 ¯ S 0 D 1 + S 1 S 0 ¯ D 2 + S 1 S 0 D 3 . (2)

The Boolean expression in equation (2) is obtained from the truth table in Table 2, which can be implemented using basic logic gates or CMOS logic. Adding more address line inputs, it is possible to switch more outputs giving 1-to-2 ⁿ data line outputs. ¹⁶ The proposed demultiplexer was also a 1 × 4 demultiplexer constructed using pass transistor logic, as shown in Figure 2. In the figure, two inverter circuits form the input point for the DEMUX. The inverters were constructed with opposite polarity Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) with their gates connected to form the input voltage V _in shown as S _A and S _B. The drain terminals of both MOSFETs were connected to form a typical output. ¹⁷ These MOSFETS were connected in such a way (complementary) that only one MOSFET conducts when the input has a low or high input voltage due to the complementary connection.

The Gate-Source voltage V _GS is equal to V _in, that is: V GS = V in … . for NMOS and the Source-Gate voltage given by V _SG is: V SG = V DD – V in … . for PMOS

Where V _DD is the supply voltage, the input voltage can have values from 0 to V _DD. When S _A = V _in = V _DD, the PMOS transistor gets cut off while the NMOS conducts and current flows to the ground terminal, and the output voltage is ‘0’. The ‘0’ volts are now applied to one of the inputs of transistor T5, which is in series with T6.

If input S _B had an input value of ‘0’ volts, the NMOS transistor inverter was cut off while PMOS conducted to give a path to the power supply and the output now had a value V _DD. The second input to transistor T5 was ‘0’. The transistor had inputs 0, 1 and gave an output ‘0’, indicating that the line D _A had been selected to distribute the input from the parity check circuit of the layered decoder circuit. Hence, the other lines D _B, D _C, and D _D were selected to feed that input for other input combinations to S _A and S _B. The input fed at line D (Y in the truth table) was distributed to any four outputs represented by D ₀, D _1, D _2, and D ₃. The distribution was based on the select inputs S ₀ (S _A) and S ₁(S _B). In Figure 2, the select lines are connected to two inverters at the first stage of the DEMUX. Each inverter created the terms given in equation (2). The inverter drove the value of S ₀, and if it was a ‘0’, then the output could be a ‘1’, similar to the S ₁ input. The following transistors drove the input to the outputs based on the bit pattern of S ₁S ₀.

The bit update circuit is an integral part of many circuits, where temporary storage and stored data updates are required periodically. These circuits have memories that will store some predetermined subset of codeword bits, though only one at a time. The circuit uses basic logic gates: the EXOR gate, a latch, and a multiplexer and inverter. It is like a loop operation, where input data bits received are fed into the multiplexer, and it is compared with the previously stored data from the latch. The EXOR gate will help identify new data and is given to the MUX, where the select inputs will ensure the new data is stored in the latch. This recently stored data is then sent to the next section of a large application circuit.

In the proposed circuit, the data input was from the DEMUX circuit, transmitting data bits received. The bit update circuit ensured that new data received was always updated and stored and then distributed through the reverse router to the parallel adder blocks in the decoder through the data bus. The bit update circuit usually works in tandem with two memories, one as an accumulator for a new data set and the other supplies the last iteration’s data. ¹⁸ These two memories act in an alternating manner. A multiplexer worked like a cross switch to facilitate their alternating operation.

The proposed bit update circuit was designed using the pass transistor logic to reduce the number of transistors. The delay needed to be reduced in the circuit, and hence the technology used was adequate. The circuit shown in Figure 3 comprises a 2 × 1 multiplexer circuit with a latch. The latch acted as the temporary storage or memory for the data bits. The data bit stored in the latch was given to an EXOR gate connected to an AND gate delay circuit. This was to create a delay so that the bits reached the multiplexer within the clock pulse. The EXOR input was also fed to MUX as one of the select inputs.

A proposed decoder architecture is described in this section, which follows the layers of component decoding. The top-level architecture is shown in Figure 4. One type of decoding technique is the layers of components decoding. It generally includes layer-by-layer processing rows of a parity check matrix. ¹⁶ Each layer is processed sequentially, and the processing of each layer depends on data processed in an immediate previous layer. Decoders using the layered technique are designed to have an inbuilt latency for processing the data between layers. By way of explanation, say if a layer in the parity check matrix needs to be processed, data processed by a previous layer need to be received initially. But it may be that these data are unavailable yet because they are still processed in the previous layer or the data bus and have yet to reach their destination. Latency such as this has an impact on the performance of the decoder. Some problems like this need to be addressed in layered decoding methods. In the proposed circuit, improvements were made to a layered component decoding approach. The method proposed used a plurality of parallel computation blocks coupled to the memory, multiple parity check blocks connected to the computation blocks, and multiple bit update blocks connected to the parity check block. Each bit update block had a memory. The received codeword split in this system, and at least one column/row was grouped and processed.

A low-density parity-check code suitable for efficient hardware implementation was designed with a belief propagation decoder circuit. Codes were arranged according to a sample H matrix whose rows and columns represented the parity check matrix. The decoder circuit had a parity check value that estimated memory, which could be arranged in groups and was logically connected to different data lengths and depths. A parallel adder generated approximate values that were fed to the parity check circuit. The new bitstream generated new values of estimates. These values generated were then stored back in the memory and fed to the bit update circuit. The bit update circuit then updated the new value for the subsequent input data received. Here, layered components decoding was performed by applying the decoding algorithm to each successive layer. Since no particular algorithm was developed, we used a standard to show how the improved decoder works. Applying a decoding algorithm for a particular layer included the use of calculations done in previous layers. The decoding was done using parallelized decoding hardware, and hence its performance may be better than the conventional approach.

The memory block was a local RAM for storing the estimates that were derived within the iteration. These estimates were stored in the memory to save the chip area. The storage memory had one output coupled to one input of the parallel adder. This was connected to the negative input of the parallel adder to provide a subtrahend for subtraction that took place in the parallel adder. The output of the parallel adder was applied to the parity check update circuitry. This block performed the updating of estimates obtained from memory for each of the parity check nodes. The output of the parity check circuit was applied back to the memory to store updated values. It was also applied to the router circuit to update the input nodes’ Log-Likelihood Ratio (LLR). The router circuitry collected multiplexers and demultiplexers that forward the appropriate estimate terms from memory to the corresponding bit update circuit. The bit update circuits were accumulators through which the current values of LLR of the input nodes were maintained from one iteration to the next iteration.

The LDPC code was within a parity check matrix H of m × j values and showed a value, H. c = 0 when multiplied by the vector c, considering the Galois field, where c was the transmitted word vector. The Galois field is a finite field that contains a finite number of elements. For each row m of the parity check matrix H, the parity check could be done as H ₁c ₁+H ₂c ₂+ … H _jc _j = 0 over the Galois field. Hence, a parity check equation, the EXOR function of ‘c’, could be written considering the rows of the H matrix having a ‘1’ in their columns.

Referring to Figure 4, soft data received was routed into the decoder system through the data bus. The received data was first routed into the bit update block. Here the data was initialized into its components of a vector. Let us assume the vector for the received data as ‘L’. We defined a set where all the bit columns for a row ‘m’ and the bits in the H matrix have a one in row ‘m’. This makes the checksum for a row over a finite field. The LDPC decoder helps detect errors in the received data when checked for every row in the matrix. When data is received, the values may not be precisely binary values of 1 or 0 but some fractional value and represented by several bits. Hence a probability of whether the bits are 1 or 0 can be represented using the LLR given by: L ( r j ) = log P ( c j = 0 ) P ( c j = 1 ) . (3)

where r _j is the input bit value.

As every input bit arrives, the estimated value is written based on the LLR. Initially, an estimate was assumed for the LLR based on the type of channel being used.

A vector ‘R _mj’ was stored in the SRAM. These were estimates stored in the SRAM after every iteration or cycle of the decoding process and the updated value in the next iteration. The memory stores a few corresponding rows of values of R _mj, representing vector R values for m rows and j columns from a parity check matrix. For every row, the vector L was written as for the checksum: L ( q m j ) = L q j ‒ R m j . (4)

The vector was then stored in the BUB. The data were fed into the reverse router block by data buses, where the data was rearranged as required by the system from the BUB. The values of the vector L were given as input to the parallel adder (PA). The other input to the parallel adder came from the memory with the values of the data stored in the form of the components of vector R. The parallel adder performed the operation approximations and subtraction of vector R from L. The results of this subtraction operation in the form of output ‘sum’ were given as input to the parity check circuit and the second set of parallel adders (PA2). A checksum, a sequence of numbers and letters used to detect errors introduced during data transmission, was carried out in the parity check block. The results of this operation were then fed to the second set of parallel adder blocks and the memory block for storage. In the PA2, the computation of the earlier subtraction (R) results and the checksum were added to regenerate the vector L. The new values of L were now sent to the router block to be rearranged into components of vector L. These values were given to the BUB to be stored for the next iteration.

The 1 × 4 demultiplexers for the LDPC decoder were constructed to have one input D and four outputs D ₀, D ₁, D _2, and D ₃. The demultiplexer had two select inputs S ₀ and S ₁. The select inputs formed the decision-maker to connect the input to a selected output. The selection was based on the four possible combinations of the select input, namely, S ₀ = 0 and S ₁ = 1, S ₀ = 0 and S ₁ = 1, S ₀ = 1 and S ₁ = 0, and finally, S ₀ = 1 and S ₁ = 1, representing the binary form 00, 01, 10, and 11. The proposed demultiplexer was simulated to check its characteristics using the Mentor graphics PADS VX.2.7 x86, a CAD tool for 180 nm technology (Open-access software that can perform an equivalent function is DSCH version 2.7for schematic design and MICROWIND version 2.0 for layout analysis).

The string of data bits was given as input D with the select inputs S ₀, S ₁ varied for the four possible combinations. The output satisfied the truth table of the demultiplexer of Table 2. It should also be noted that the voltage rises and falls in Figures 5(a) to 5(c), which are not exactly zero or one. There was a distortion of the signal, but it showed a considerable voltage level to be read as 0 or 1. The voltage variation of 1V, 1.3V, and 1.5V did not significantly affect the output waveforms with only a slight variation in the peak voltage values.

The waveforms shown in Figures 5(a) to 5(c) represent the distribution of bits received from the adder circuit (refer to Figure 4). The data’s choice is based on S ₀ (S _A) and S ₁ (S _B). The waveforms of D ₀, D ₁, D _2, and D ₃ also show the effect of the gates’ switching characteristics, and the peak voltage drops, which is slightly due to the capacitive effect at the input nodes. As the output voltage increases in time, the biasing voltages decrease. A decreasing value of the gate-source voltage reduces the charge density and reduces the output voltage, which does not reach V _DD.

The output voltage was seen to have a delay in reaching the final voltage. This was due to the parasitic capacitance, the gate channel capacitance between the gate-source and gate-drain terminals. Any switching action in the device leads to the formation of parasitic capacitance. A sudden change of voltage from zero to a high value creates a capacitive effect which can be realized as an RC circuit. Resistance is created, and the device consumes more power to drive the circuit, which depicts a delay in the device’s output voltage. It creates a delay when it drives zero loads. The parasitic delay grows linearly with the number of inputs. This effect was seen in the waveforms for the demultiplexer, which displayed a slow increasing ramp voltage. According to simulation result, the demultiplexer area is 10.5 × 25.555 μm ².

The reverse router had a multiplexer to transmit data bits from the bit update circuit to the parallel adder through the data bus. The characteristic of the multiplexer was to choose a particular input to be connected to the output. The selection of the input was based on the two select signals. In Figure 3, the schematic of the multiplexer is shown. The multiplexer had four inputs I _A, I _B, I _C, and I _D, and a single output Z. The select inputs were S _A and S _B. Hence the multiplexer was a 4 × 1 MUX. Since there are only two select lines, the possible input lines were four, and the possible combination was S _BS _A = 00, S _BS _A = 01, S _BS _A = 10, and S _BS _A = 11. In line with the truth table in Table 1, if S _B = 0 and S _A = 0, the line selected would be I _A since the combination 00 is for I ₀(I _A) line. The schematic in Figure 3 is simulated using the test bench. The 180 nm technology was used for the simulation and voltage values of 1 V, 1.3 V, 1.5 V, and 2.5 V. The output observed satisfied the truth table, Table 1. Here the threshold voltage loss restricts the output voltage to the range [0V, V _DD – V _Tn].

The proposed multiplexer circuit was simulated for voltage versus time using 180 nm for input voltages of 1 V, 1.3 V, and 1.5 V, and the output waveforms are shown in Figures 6(a) to 6(c), respectively. Figures 6(a) to 6(c) show the output voltage of the selected input to be given to the output. Even though the output waveform represented the correct selected input, it delayed reaching the maximum voltage. For some inputs, it did not reach the minimum zero value. It was the delay caused by the inverter, and the threshold voltage loss restricted the maximum voltage. Charging the output for a logic one voltage was very slow compared to the transition to a logic 0. The parasitic capacitance increased the charging time from low to high since it was diverted from the output node. The charging of the output capacitance was time-dependent and began as linear as (t/2τ _n) and then levelled out.

Since V _out(t) increases in time, the device bias voltages V _GS – V _DD – V _out (t) = V _DS decreases with time. A decreasing value of V _GS reduces the channel charge density, while smaller V _DS shows a reduction of the drain-source electric field. This indicates that it is difficult to pass a logic 1 voltage through the n-channel transistor. The spikes seen in the output were caused due to the capacitive coupling of the input to the output by the gate-drain capacitance. As the input suddenly increased from 0 V to V _DD, the capacitance did not have enough time to drop its voltage instantly. Hence, it would have retained some amount of charge and is seen as spikes of voltage. The proposed multiplexer circuit area is 9.9 × 32.155 μm ².

The multiplexer and demultiplexer circuits were simulated using the SilTerra CEDEC pyxis project of the Mentor graphics CAD tool PADS VX.2.7 x86. The simulation environment was an input voltage value of 1 V, 1.3 V, and 1.5 V for 180 nm technology, tabulated in Table 3. The results showed a low power dissipation in nanowatts. This is because of pass transistor logic, which reduced the number of transistors used and is reflected in the results. A reduced number of transistors (12, 14) led to lower power dissipation and reduced layout area. The delay is only 80 ns and 130 ns for DEMUX and MUX, respectively.

Table 4 shows a comparison of the proposed circuit with various published research. It can be seen that the proposed circuit performs better. In terms of power dissipation, the proposed multiplexer circuit has a power dissipation of 7.067 nW, whereas Bousseaud and Negra ⁷ had a value of 5 mW. The approach used by Bousseaud and Negra ⁷ used a transmission gate, while pass transistor logic is used in the proposed circuit. Pass Transistor Logic (PTL) does provide an advantage in the design of circuits with the elimination of redundant transistors. When the number of transistors was reduced, it had a lower power dissipation as each transistor occupied some area and dissipated power. For the DEMUX circuit, the power dissipation produced by Saseendran and Mehra ⁶ had a value of 142 uW, and for the proposed circuit, it was 5.14 nW. The input voltage also tended to be at a lower value of 1.5 V. There was a huge difference in the number of transistors used in the design.

The bit update circuit received new data and then arranged them into its vectors and routes them to the multiplexer as input to the parallel adder. In each iteration of the decoder circuit, the bit update circuit restored new data values after rewriting the data received from the router circuit with data from the transmitter received through the data bus. The bit update circuit was simulated for voltage versus time using 180 nm for input voltages of 1 V, 1.3 V 1.5 V, and 2.5 V, and the output waveforms are shown in the Figures 7(a) to 7(d), respectively.

Figures 7(a) to 7(d) depict the output obtained for the bit update circuit. The arrival of the clock signal at the input nodes caused clock skew due to the capacitive coupling effect. At the output of 1.5V, it can be observed that the waveform has glitches. Glitches are temporary changes in the value of the output. They were caused due to the skew in the input signals to the gate of the transistor. Glitches can be reduced by gate sizing and path balancing techniques. Propagation of glitches can be reduced by using a smaller number of inverters, which tend to amplify and propagate glitches. At a higher voltage of 2.5 V, the output showed a smooth and expected waveform. The area of the bit update circuit is 46.42 × 14.62 μm ².

The whole LDPC circuit was designed according to Figure 4. The components added to the test bench would be the V _DD, the ground terminal (GND), DC, and pulse. The DC was the input voltage of 1 V, 1.3 V, and 1.5 V. We needed to set the delay (1ns), initial value (0 V), period (50 ns), the pulse value and the rise time and fall time, and the width of the pulse. The bit pattern to be run through the decoder was also specified. The proposed decoder circuits were simulated for voltage vs. time effect on the output voltage for different input voltages, as shown in Figures 8(a) to 8(c). The input voltages used were 1 V, 1.3 V, and 1.5 V at 180 nm technology.

The carry inputs to the second set of parallel adders are also shown as check 0 to check 3. The output was measured at various points of the circuit, that is, the output of the memory unit (Vo1), the output of the adder (Vo2), the output of the parity check (Vo3), the output of the router (Vo4), and the final at the reverse router (VoF). It was observed that at the initial points of the check, the output voltage did not suffer from any loss of signal. As the circuit became larger, all effects of power loss come into play due to the different circuits. At the final output (VoF), glitches were observed at regular intervals. This happened to off-pass transistors where the source and drain were initially high and then pulled low. The output of the router circuit shows the waveform reached the peak voltage but did not reach the zero line. This represents the presence of some minimum voltage that did not allow the voltage to reach zero. Practically, the drain current of a CMOS transistor does not reach zero once the voltage of the gate terminal goes below the threshold voltage.

These values are the most updated: the parity check unit block (PUCB) and the values used for the next iteration. ²³ The flow of data into the circuit with the input of received data at the bit update circuit was tested with bits of data given using the rows from a standard H matrix. Every stage of the movement of the bits through each layer, namely bit update, reverse router through the data bus to parallel adder one and from the adder to the parity check block, a second set of the parallel adders, and the stored data in the memory has been simulated and outputs observed.

The results of individual layers and the entire decoder are tabulated in Table 5. Various input voltages were given to observe the effect on the decoder. The decoder circuit designed achieved low power dissipation and a reasonable delay improvement.

In Table 6, the obtained results for the LDPC decoder are compared and analyzed with other published work.

The proposed circuit performed better in power dissipation than work done by Lee et al. ²¹ The power dissipated by the proposed circuit is in nanowatts, while all references are in milliwatts (19, 21). This may be because the proposed circuit was designed using pass transistor logic, which reduced the number of transistors. CMOS circuits dissipate power during switching times.

Hence, reducing the switching activity reduced the power dissipation. Other studies ^{19 – 21} achieved 7.92 Gbps, 3.9 Gbps and 1956.5 Mbps for 90 nm, 65 nm, and 90 nm technology, respectively. The proposed circuit simulated for 180 nm obtained the throughput 12.184 Mbps, 12.496 Mbps, and 12.496 Mbps for input voltages of 1V, 1.3V, and 1.5V. The throughput didn’t give a better value because the circuit was designed to function well at lower voltages, which is a trade-off with low supply voltage, lower power dissipation, and smaller area with throughput. We used 1V, 1.3V, and 1.5V, and performance at 1.5V was much better in power dissipation and throughput. At lower voltages, the noise margin becomes critical. The area of the proposed circuit is in nanometres squared, which is also reduced compared to Bhargava et al. ²¹ ( Table 6).