In the digital filters, the block processing concept increases the throughput of the architecture. If the input block size is ‘ N ’, the filter produces ‘ N ’ outputs per one iteration, which means N -times throughput increases. The input matrix X n 1 n 2 is needed at different systolic stages to generate a 2-D filter output Y n 1 n 2 is of the length of the filter ( L). ³ X n 1 n 2 = x n 1 n 2 x n 1 n 2 − 1 x n 1 − 1 n 2 x n 1 − 1 n 2 − 1 . . . . . . . . x n 1 n 2 − L + 1 x n 1 − 1 n 2 − L + 1 . . . . . . x n 1 − L + 1 n 2 x n 1 − L + 1 n 2 − 1 . . x n 1 − L + 1 n 2 − L + 1 (Eq. 1)

Let us consider x n 1 n 2 − m is the m + 1 th input of the 2-D FIR filter, w p q represents filter coefficients. The m + 1 th output of the filter is expressed as ³ : Y m n 1 n 2 = x n 1 − p n 2 − m − q . w p q p = 0 L − 1 q = 0 L − 1 (Eq. 2)

w p q is expressed as equation (3). ³ w p q = w 0 0 w 0 1 w 1 0 w 1 1 . . . . . . . . w 0 L − 1 w 1 L − 1 . . . . . . w L − 1 0 w L − 1 1 . . w L − 1 L − 1 (Eq. 3)

Thus, the 2-D FIR filter block output at each systolic stage is expressed as ¹¹ : Y = G n 1 n 2 . w p T p = 0 L − 1 (Eq. 4)

The filter coefficient vector required at each stage is expressed as ¹¹ : w p = w p 0 w p 1 w p 2 … w p L − 1 1 XL (Eq. 5)

Each iteration of the 2-D block FIRA needs the parallel calculation of a block of input samples and produces a block of output. At each systolic stage, a set of L − 1 delayed inputs is required to generate a block of input. The input pixels at p + 1 th the stage is represented by G n 1 n 2 , which is given in matrix form as ¹¹ : G n 1 n 2 = x n 1 − p n 2 x n 1 − p n 2 − 1 x n 1 − p n 2 − 1 x n 1 − p n 2 − 2 . . . . . . . . x n 1 − p n 2 − L + 1 x n 1 − p n 2 − L . . . . . . x n 1 − p n 2 − N + 1 x n 1 − p n 2 − N . . x n 1 − p n 2 − N − L + 2 (Eq. 6)

To facilitate parallelism, we further decompose the input pixel matrix G n 1 n 2 and coefficient vector by a factor of s. The input pixel matrix G n 1 n 2 is decomposed into L S sub matrices represented as X p q of dimension G N X S , and also the coefficient vector w p q of dimension 1 X S ; 0 ≤ q ≤ L S − 1 . Equation (4) is modified as ¹¹ Y NX 1 = X p q w p q T q = 0 L s − 1 p = 0 L − 1 (Eq. 7)

Where ¹¹ X p q = x u v x u v − 1 x u v − 1 x u v − 2 . . x u v − 2 x u v − 3 . . x u v − 3 x u v − 4 . . . . . . x u v − N + 1 ) x u v − N x u v − N − 1 x u v − N − 2 (Eq. 8)

w p q = w p sq w p sq + 1 … w p sq + q − 1 , u = n 1 − p and v = ( n 2 − sq ). Equation (7) is re-writtenas Y NX 1 = y p q q = 0 L S − 1 (Eq. 9)

Where y p q = X p q w p q T p = 0 L − 1 (Eq. 10)

The symmetry concept is considered for the reduction of complex multipliers. In this paper, two types of symmetry, Diagonal Symmetry Filter (DSF) and Quadrantal Symmetry Filter (QSF) ^{7 , 8} for 2-D FIRAs, are studied and explored. The following transfer functions are used to design the two types of symmetries in the 2-D FIRA. ^{7 , 8} A)

DSF 2-D FIR Filter: The transfer functions of DSF in magnitude response as H z 1 z 2 = H z 2 z 1 , where z 1 = e j θ 1 and z 2 = e j θ 2 , ∀ θ 1 , θ 2 . The filter coefficients are related as h ij = h ji for all i , j . Equation (11) expresses the transfer function of diagonal symmetry. ¹⁷

The general filter coefficients and two types of symmetry coefficient matrices are shown in Figure 1.

The proposed work implements two efficient symmetrical 2-D FIRAs and one generic filter architecture. Because of the symmetry of the filter coefficient, fewer multipliers are needed to design the filter.

A LUT is treated as memory in memory-based multiplication, and the precomputed outputs of filter coefficients are saved in the LUT. DA multiplication is the process of shifting and accumulating LUT output values. The input sample and coefficient are multiplied in the process of memory-based multiplication. The LUT memory can save 2 ^w possible values for the binary input of word length of w bits and a coefficient of bit length of c bits. In the process of standard LUT-based multiplication, it requires 2 ^w words to save the precomputed partial products in LUT.

Even multiples can be obtained from memory using left shift operations on odd multiples. This work uses (2 ^w/2) words to save the odd multiples of coefficient C. This approach is shown for w = 4-bits of input sample in Table 1. In this table, the 8-address locations are stored by odd multiples of coefficient C, such as C, 3C, 5C, 7C, 9C, 11C, 13C, and 15C. Even multiples are evaluated using left shift operations of C, such as 2C, 4C, and 8C by 1-, 2-, and 3-times left shift operation to C, respectively. Next, 6C and 12C products are produced by a left shift of 3C; the remaining 10C is derived from 5C, and 14C is derived from 7C, respectively. The product output for the input sample consists of all zeros x = 0000 produced by resetting the LUT.

The single-port MLUT-DA multiplier is realized with reference to Table 1, as shown in Figure 2A. The structure has one 4-to-3 encoder block, one 3-to-8 decoder block, one control logic to produce Reset (RST), and control lines {S0, S1} to accommodate the shifts required for the computation of even multiples of coefficients such as 2C, 4C, 8C, 10C, 12C, and 14C. A maximum of three shifts are required, so two bits of control signals are contemplated in the structure.

Using a control logic block, the RST is formed from the applied input sample. It results in eight odd multiples of coefficients with c + 4 bits. An extra 4 bits are essential to computing the highest odd multiple value 15C is precomputed and stored in the LUT. The decoder output corresponding location is read and fed to the NOR cell, which is made up of c + 4 NOR gates with one common input of RST. The NOR cell outputs are shifted by a barrel shifter based upon the control signals {S0, S1} coming from the control logic. The barrel shifter has 2 × (c + 4) AOI (AND_OR_INVERT) gates or 2 × 1 multiplexers (MUXs). Finally, the barrel shifter output is the multiplication result of the input sample and coefficient.

The combinational logic expression of the 4-to-3 encoder, employed in the LUT multiplier, is indicated in equations (13), (14), and (15). A 0 = x 0 x 1 ¯ . x 1 x 2 ¯ ¯ . ( x 0 + x 2 x 3 ) ¯ ¯ (Eq. 13) A 1 = x 0 x 2 ¯ . ¯ ( x 0 + x 1 x 3 ) ¯ ¯ (Eq. 14) A 2 = x 0 . x 3 (Eq. 15) where A ₂ A ₁ A ₀ are address bits derived from the actual input bits x ₃ x ₂ x ₁ x ₀. The control logic signals (RST and S0, S1) are given by equations (16), (17), and (18). S 0 = ( x 0 + x 1 + x 2 ¯ ¯ ) ¯ (Eq. 16) S 1 = ( x 0 + x 1 ) ¯ (Eq. 17) RST = ( x 0 + x 1 ¯ ) . x 2 + x 3 ¯ (Eq. 18)

In very large scale integration (VLSI) design, the conventional multipliers consume more power and occupy more area, whereas the LUT-based multipliers save area and power consumption. Hence, a further reduction in the hardware is achieved by LUT-DA multipliers.

In the LUT, only the even multiples of the coefficients are saved. Hence, only 2 ^w/2 words are required instead of all 2 ^w words. Even multiples can be translated into odd multiples by adding one filter coefficient magnitude. The barrel shifter and encoder blocks are not required for this modified multiplier, and one 2 × 1 MUX is required to choose the odd or even-multiple coefficients. Table 2 depicts the even multiples storing technique for w = 4. The even values of constant-coefficient 0 2 C 4 C … 12 C 14 C are precomputed corresponding to x 3 x 2 x 1 using the 3-to-8 decoder and saved in the 8-LUT locations. The other input for the 2 × 1 MUX is the LUT even output, and the other input is the odd output from the adder. The selection lines of the MUX are the least significant bit LSB-bits of the input sample x 0 . Whether the coefficients are even or odd multiples depends on the input sample’s LSB bit. Figure 2B represents the modified LUT-based multiplier.

Likewise, odd multiples of the coefficient can be saved in an improved LUT-DA multiplier by using a subtractor to generate the required even multiples. In the proposed work, the SPLUT multiplier is converted into a DPLUT multiplier using the DA approach. When the input sample bits are more, the dual-port memory helps decrease the LUT size. The common filter coefficient is multiplied simultaneously with two separate input samples using a DPMLUT-based multiplier. The following section explains how the proposed filters use an improved MLUT-DA multiplier with even multiples storage.

The block-based 2-D FIRA is shown in Figure 3 for L = 4, with N = 2 without any symmetry, and is considered a general filter. The input samples {x _k ⁰, x _k ¹} are from the same row of the image input matrix given to the shift register unit (SRU) array, and input samples are given in serial order, block by block and row by row. The SRU array contains L − 1 SRUs, each with L shift registers with M words. Here, SRU1 is termed as {SR1, SR2}. Likewise, SRU2 and SRU3 are placed in an array form considered the SRU array for order L = 4. Each L - Delay Unit Block (DUB) produces NL samples by applying each set of past N and present samples to the total L sets.

The input block of L input samples from the image matrix M × M are applied as present inputs. The ( L − 1 ) SRU array receives these parallel inputs. Figure 4A represents the structure of SRU using the L number of registers. The present input sample and the past input sample blocks are applied to the N -DUBs of the DUB array. Each DUB consists of ( L − 1 ) flipflops. It produces the present and past samples required for block processing. As shown in Figure 4B, each DUB generates LN samples. The L-DUBs give the L × LN of input samples to the filter’s arithmetic module.

Structures of block-based symmetric 2-D FIR filter arithmetic modules

This section explores two symmetry-type 2-D FIR filters and one general filter of L = 4 with N = 2.

General filter structure with MLUT multipliers

The arithmetic module of the general filter architecture is realized by the L number of Processing Units (PU) and an Adder Tree (AT) block, which receives LN samples from DUB.

Each PU block is constructed by N number of Product Cells (PC), which are used to multiply the input sample by the corresponding filter coefficients. Generally, the product is done by conventional multipliers. MLUT multipliers are used in place of these power-hungry conventional multipliers. At last, the AT adds the outputs of the PU block and generates the N filter outputs corresponding to the N block of inputs.

This general filter architecture is modified by DPMLUT multipliers, as presented in Figure 5. In this architecture, the inputs multiplied with the common filter coefficients are given to a DPLUT-multiplier. Hence, a total of L × L DPLUT multipliers are needed to process the complete multiplication of input samples of L = 4 and filter coefficients. 2 L × L multipliers are needed if SPLUT-based multipliers are used. The DPLUT-based multipliers save 50% of the area compared to SPLUT multipliers. Each DPLUT-based multiplier produces the L number of filter outputs. Total L memory multipliers generate L × L N number of outputs, and these are parallelly added by N -AT blocks and give N outputs with a size of ( c + 4 )-bits.

In this work, the multiplier quantity is decreased by symmetry in the filter coefficients. Two different symmetries are described in this section, and these symmetry filters can be used to design circular symmetry, fan-type and diamond filters.

Structure of 2-D FIR Diagonal Symmetry Filter (DSF)

In the DSF coefficient matrix, the sixteen coefficients are reduced to ten, such as { h 00 , h 01 , h 02 , h 03 , h 11 , h 12 , h 13 , h 22 , h 23 , h 33 } for L = 4 as shown in Figure 1B. Figure 6 represents the arithmetic module of the DSF-based 2-D FIRA, and it is designed by diagonal symmetry. Before the multiplication process, the input samples to be multiplied with common filter coefficients are added.

For the one input of N = 2, seven adders are required to accumulate symmetry input samples. The seven highlighted colored adders indicate the adders for the other input sample. The adder is a simple block than the multiplier. The diagonal symmetry filter requires 2 L + 2 N multipliers instead of L × L N , but extra L − 1 N adders are required. Next, these 2 L + 2 N multipliers are only designed for 2 L + 2 N / 2 DPLUT-based multipliers. Hence, half of the area is optimized. Finally, all the multiplier output samples are accumulated by N - AT blocks to produce N outputs.

Because multipliers are responsible for most of the power consumption, DPLUT-based multipliers are used to optimize them. Hence, ten DPMLUT multipliers are needed to produce the N = 2 outputs from the diagonal symmetry filter. The DSF architecture for L = 4 with N = 2 needed 20 individual SPLUT multipliers.

DPLUT decreases the LUT size for input samples with greater bit lengths by adding an additional shifter. Because of parallel block processing, two inputs are multiplied with the common filter coefficient in a 2-D FIR filter. This concept can be used to replace two SPLUT multipliers with a single DPLUT multiplier. The internal structure of the conventional DPLUT-based multiplier and the modified DPLUT-based multiplier are shown in Figure 7A and B.

The common filter odd coefficient multiples are precomputed and placed in the LUT memory. According to the input bits, the address of the location in the LUT is determined by the address encoder and address decoder. DPLUT fetches the corresponding locations based on the given addresses of two ports and provides two parallel outputs. Furthermore, each output is shifted by barrel shifters after passing through the corresponding NOR gate. The control lines for shifting are generated from the input sample bits handled by some control circuit logic, as explained earlier.

This conventional DPLUT-DA multiplier has been revised, shown in Figure 7B for w = 4 bits of input sample using even multiples storage in LUT. It can be observed that the modified even multiples storage LUT-DA multipliers need less memory and area. Control logic for RST, barrel shifter, NOR cell, 4-to-3 encoder, and control signals of barrel shifter s o s 1 are not needed to enhance the DPLUT multiplier, and this feature reduces area further.

The conversion of SPLUT into DPLUT is a critical task. The common filter coefficients stored in the LUT must be shared by two inputs simultaneously. For this, the control logic is introduced related to the clock signal to choose the address locations with a slight delay. Figure 8 represents the control logic using multiplexers for a DPLUT-DA multiplier.

Structure of a 2-D FIR Quadrantal Symmetry Filter (QSF)

The QSF consists of eight unique filter coefficients are given as { . h 00 , h 01 , h 02 , h 03 , h 10 , h 11 , h 12 , h 13 . }. Figure 9 represents the architecture of QSF for L = 4 with N = 2. A total of 16 SPLUT multipliers are needed for this structure, and it is modified with eight DPLUT multipliers to produce N -block outputs.

The summary of the number of single-port and dual-port multipliers needed for each symmetry is presented in Table 3.

Experiment/validation

This section analyzes the implementation and results for the proposed 2-D FIRAs. Multipliers, registers, and adders construct the architecture of the proposed filters. The hardware block's complexity depends on the filter input sample bits, length L , input block size N , and filter coefficients. Hence, DSF and QSF symmetry-based 2-D FIR filters are designed and explored to reduce the quantity of the multipliers. Next, the multiplier architectures are optimized by dual-port even multiples storage LUT- based multipliers. The architectures are synthesized using the Genus Synthesis tool-19.1 in 45nm technology with a generic library of Cadence vendor constraints. There is a free synthesis tools available like Xilinx Integrated Synthesis Environment, which can be used instead of Genus Synthesis tool in Cadence to replicate our methods. Power consumption of architectures is calculated with an image size of 64 X 64 and at 20 MHz frequency. The synthesized results (reports in Underlying data ²⁷ ) have been analyzed and compared with the existing architecture’s results. All Verilog code associated with the work is available in Software availability. ²⁸