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Research Article

Design of a High Efficiency Switched-Capacitor (SC) DC-DC Converter

[version 1; peer review: 1 approved with reservations, 2 not approved]
PUBLISHED 19 May 2022
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Abstract

Portable electronic devices and miniaturized devices would require different operating voltages and load current which can be powered through DC-DC converter. In this paper, the proposed converter is based on a multiple topology of DC-DC converter circuit for more than one voltage gain regions using switched capacitor (SC) method. The post layout implementation showed that the high efficiency networks are achieved with low voltage drop and low internal resistance. The efficiency of 95% and 85% are shown, on the networks in the 1/2 and 2/3 voltage gain regions respectively, proving that this method is advantageous compared to other literature papers.

Keywords

High-efficiency, DC-DC converter, switched-capacitor method

Introduction

Portable electronic devices such as mobile phones have become smaller and more compact. This evolution has led to smaller battery size that require less voltage than its previous version.1 There is also a growth of applications in wearable technology to enhance the quality of life through healthcare, education, security and many more.25 As wearable designs grow, power and battery management become crucial, therefore there is a need to extend the battery life of a wearable design by employing energy efficient, while boosting circuit blocks. Different loads in the miniaturized wearable devices would require different operating voltages and load current which can be powered by battery through DC-DC converters. Converters are needed to regulate the voltage to the device requirement. There are two main types of converters which are electronic conversion and magnetic conversion.6 Electronic conversion uses switching technology, while magnetic conversion utilizes magnetic field property in an inductor or a transformer. Most of the step-down DC-DC converters used in the system are buck converters. As the devices become smaller, a buck converter seems to be bulky, and its electromagnetic field becomes noisy due to the present of inductor in the circuit.7 Magnetic field noise is bad for communication devices such as cell phones and laptops.8 It also requires more components to build the circuit such as capacitor, diode, transistor as switch and sometimes it requires a filter to operate. Some of the problems include the size of buck converter, which is bulky due to multiple electronic components, compared to switched-capacitor converter. As for the inductor-based converter, it is dominantly noisy with magnetic field effects.

The focus of this project is to design a step-down converter circuit based on the switched-capacitor method which is smaller and cheaper. The design also focused on how to achieve higher efficiency to make it competitive compared to conventional inductor-based converter. This project also aims to minimize the number of electronic components used to reduce the cost. The project aims to use only capacitor and transistor as a switch in the circuit.

Methods

This section describes the methods used to complete the project including the design flow of the network, the circuit design, and the Electronic Design Automation (EDA) tools used. The design flow of this project is shown in Figure 1. The circuit is designed using complementary metal-oxide semiconductor (CMOS) 0.5um process using open-source EDA tools, namely LTSpice® software tool for schematic simulation and Electric very large-scale integration (VLSI) design tool for layout implementation.

fa547084-fda8-41ec-8906-4e982f34bfda_figure1.gif

Figure 1. Design flow of the project.

The circuit or network as shown in Figure 2 has been designed using Kirchhoff Voltage Law (KVL) method,9 which was divided into two phases: common phase and discharge phase. Common phase is the phase where the capacitor is charged and connected in parallel, while in discharge phase the capacitor is connected in parallel for the 1/2 gain region and in series for the 2/3 gain region.

fa547084-fda8-41ec-8906-4e982f34bfda_figure2.gif

Figure 2. The SC DC-DC converter.

Table 1 shows the switch cycle when the switches (S1 – S10) are turned on or off depending on the phase and gain regions.

Table 1. The switch cycles.

SwitchCommon phaseGain phase
G = 1/2G = 2/3G = 1
S11000
S20111
S30001
S41000
S50100
S60010
S71001
S80100
S91000
S100110

Results and discussion

This section discusses the results obtained in this project and compares these results to those of previous study findings.1012 Simulation results of the post layout implementation show that the high efficiency networks are achieved with low voltage drop and low internal resistance. The efficiency of the network is calculated and compared with other literature papers as shown in Table 2. In this work, efficiency is calculated based on the following equation.13

Efficiency=Obtained outputExpected output

Table 2. Table of comparison.

GainEfficiency (to)
This workNetwork10Network11Network12
1/29581.9578.7880.54
2/38580.5173.2075.81

The method is shown to be advantageous over previously developed analysis methods because of its simplicity.

From Table 2, the efficiency of this work or network is the highest compared to the other networks. The designed network used much less CMOS transistors compared to other networks. Hence, the designed network produced lower voltage drop across the transistor.

Conclusion

A multiple gain topology of DC-DC converter circuit for networks in the 1/2 and 2/3 voltage gain region using switched capacitor method has been designed with efficiency of 95% and 85%, respectively. This method has shown to be advantageous over previously developed analysis methods because of its simplicity. The network/circuit can be further improved by implementing clock cycle controller to control the phase of the clock in order to reduce any uncertainty at the output.

Data availability

All data underlying the results are available as part of the article and no additional source data are required.

Ethical approval

The authors declared that no human or animal experiments were involved in supporting this work.

Author’s contribution

Ahmad Khawarizmi performed data curation, formal analysis, investigation, methodology, software, validation, visualization, writing – original draft preparation. L. Lee performed conceptualization, data curation, methodology, project administration, resources, software, supervision, writing – original draft preparation, writing – review & editing.

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Khawarizmi A and Lee L. Design of a High Efficiency Switched-Capacitor (SC) DC-DC Converter [version 1; peer review: 1 approved with reservations, 2 not approved]. F1000Research 2022, 11:541 (https://doi.org/10.12688/f1000research.73393.1)
NOTE: If applicable, it is important to ensure the information in square brackets after the title is included in all citations of this article.
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Open Peer Review

Current Reviewer Status: ?
Key to Reviewer Statuses VIEW
ApprovedThe paper is scientifically sound in its current form and only minor, if any, improvements are suggested
Approved with reservations A number of small changes, sometimes more significant revisions are required to address specific details and improve the papers academic merit.
Not approvedFundamental flaws in the paper seriously undermine the findings and conclusions
Version 1
VERSION 1
PUBLISHED 19 May 2022
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Reviewer Report 12 Oct 2023
Jéssika Melo de Andrade, Department of Electrical Engineering, Federal University of Santa Catarina, Florianopolis, Brazil 
Not Approved
VIEWS 1
The introduction needs to further explore the gain techniques in the literature and more recent references should be used.

The topology proposed in the paper needs to be further explored statically, description of the converter operation, design ... Continue reading
CITE
CITE
HOW TO CITE THIS REPORT
Melo de Andrade J. Reviewer Report For: Design of a High Efficiency Switched-Capacitor (SC) DC-DC Converter [version 1; peer review: 1 approved with reservations, 2 not approved]. F1000Research 2022, 11:541 (https://doi.org/10.5256/f1000research.77041.r186484)
NOTE: it is important to ensure the information in square brackets after the title is included in all citations of this article.
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Reviewer Report 12 Oct 2023
Yugal Kishor, National Institute of Technology, Raipur, Raipur, India 
Not Approved
VIEWS 2
  1. Lack of technical content, i.e. there no equivalent circuit diagram in different operating modes. 
     
  2. There is no clarity on input and output voltage range.
     
  3. There is no
... Continue reading
CITE
CITE
HOW TO CITE THIS REPORT
Kishor Y. Reviewer Report For: Design of a High Efficiency Switched-Capacitor (SC) DC-DC Converter [version 1; peer review: 1 approved with reservations, 2 not approved]. F1000Research 2022, 11:541 (https://doi.org/10.5256/f1000research.77041.r204811)
NOTE: it is important to ensure the information in square brackets after the title is included in all citations of this article.
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2
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Reviewer Report 12 Oct 2023
Divya Navamani J, SRM Institute of Science and Technology (Deemed to be University), Kattankulathur, Tamil Nadu, India 
Approved with Reservations
VIEWS 2
  1. Efficiency analysis is not clearly presented. The main objective of this work is high efficiency. So they need to extend the work. 
     
  2. Circuit diagram is not clear.
     
... Continue reading
CITE
CITE
HOW TO CITE THIS REPORT
Navamani J D. Reviewer Report For: Design of a High Efficiency Switched-Capacitor (SC) DC-DC Converter [version 1; peer review: 1 approved with reservations, 2 not approved]. F1000Research 2022, 11:541 (https://doi.org/10.5256/f1000research.77041.r193767)
NOTE: it is important to ensure the information in square brackets after the title is included in all citations of this article.

Comments on this article Comments (0)

Version 1
VERSION 1 PUBLISHED 19 May 2022
Comment
Alongside their report, reviewers assign a status to the article:
Approved - the paper is scientifically sound in its current form and only minor, if any, improvements are suggested
Approved with reservations - A number of small changes, sometimes more significant revisions are required to address specific details and improve the papers academic merit.
Not approved - fundamental flaws in the paper seriously undermine the findings and conclusions
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